1. Field of the Invention
The present invention relates to crosspoint switching of electronic signals and, more particularly, to a switched-transconductance circuit having integrated T-switches for use in a crosspoint switch.
2. Discussion of Related Art
A simple crosspoint having four inputs and four output channels (i.e., a 4.times.4 crosspoint) is shown in FIG. 1. Each input 20 receives an input signal (e.g., an audio, video or other electronic signal) and each output 22 provides an output signal. The making or breaking of each crosspoint connection 24, determines the content of the output signals at each of outputs 22. Such a crosspoint could be used, for example, to switch video signals into a computer or otherwise to permit the selection of outputs from a variety of different input sources, e.g., video from cable sources or audio from tape decks, receivers or compact disc players. Since each output 22 typically is driven by only one input 20, each output 22 of the crosspoint of FIG. 1 could be considered to be an output of a four-to-one (4:1) multiplexer. In fact, a common method of implementing an n-by-m (n.times.m) crosspoint is to interconnect "n" corresponding inputs of "m" n-to-1 (n:1) multiplexers.
It typically is desirable for the connections, e.g., connections 24 in FIG. 1, to be made or broken at high speeds, thereby necessitating purely electronic (as opposed to electromechanical) switching at each of the connections. Thus, prior art crosspoints have employed transistors as switches at each connection of a crosspoint. Parasitic capacitances of simple transistor switches, however, may allow high frequency input signals to pass through to unselected outputs. This phenomenon is known as "crosstalk" between channels.
One circuit employed to reduce crosstalk between an input to and an output from a switch is shown in FIG. 2. This circuit commonly is referred to as a "T-switch." As shown, the T-switch has an input 20 to receive an input signal and an output 22 to provide an output signal. Input 20 and output 22 could correspond, respectively, for example, to one of the inputs and one of the outputs of the crosspoint shown in FIG. 1.
Select line 26 activates or deactivates the T-switch. When select line 26 is high, transistors M1 and M2 are turned on and transistor M3 is turned off. Hence, when select line 26 is high, i.e., has a voltage thereon that is above a predetermined threshold voltage (e.g., three volts), the T-switch is activated since a low impedance path, i.e., including only to the "on" resistance of transistors M1 and M2 in series, is provided (via transistors M1 and M2) between input 20 and output 22, thereby permitting a signal at input 20 to be provided at output 22. Conversely, when select line 26 is low, i.e., has a voltage thereon that is below a predetermined threshold voltage (e.g., three volts), transistors M1 and M2 are turned off and transistor M3 is turned on. Thus, when select line 26 is low, the T-switch is deactivated since the impedance of the path from input 20 to output 22 is very high in this state, i.e., the impedance is equal to the "off" impedance of transistors M1 and M2 in series.
When the T-switch is deactivated, however, although the parasitic capacitances of transistors M1 and M2 are present (permitting high frequency input signals, e.g., greater than one megahertz (MHZ), to reach node 28 of the T-switch), transistor M3 provides a low impedance path from node 28 to ground node GND, i.e., a constant voltage node. Therefore, when the T-switch is deactivated, much of the unselected input signal that normally would pass through to the output (resulting in crosstalk between the unselected input and the output) is shunted from node 28 to ground. The transfer function of such a T-switch is that of a two-pole high pass filter, as compared to the single pole (high-pass) transfer function of a more simple single transistor switch. The filtering provided by a T-switch configuration therefore may significantly improve the low frequency isolation between the inputs and outputs of a crosspoint in which such T-switches are employed.
Such a T-switch implementation of a crosspoint results in negligible static power dissipation (limited by transistor leakage), zero offset between the input and output, and a large input signal range, i.e., approximately one transistor threshold voltage (Vt) above and below, respectively, the low and high power supply voltage rails of the circuit. Since the T-switch is bidirectional (due to its symmetry), however, the input source is directly coupled to the output load when the T-switch is activated. Because the inputs are directly coupled to the outputs, the number of outputs to which an input may be fanned out is limited, especially if the output loads are resistive. In addition, the bidirectional nature of T-switches typically necessitates a break-before-make switching sequence so as to avoid the momentary shorting of input sources together when switching channels.
When metal oxide semiconductor (MOS) transistors are used in T-switches, the pass transistors, e.g., transistors M1 and M2 in FIG. 2, can introduce significant distortion in the transfer function between an input and an output. This distortion results because the "on" resistance of an MOS transistor varies with the gate-to-source voltage (Vgs) and the drain-to-source voltage (Vds) of the transistor. In a CMOS process, this variation in "on" resistance can be reduced by placing an n-channel device in parallel with a p-channel device and driving the gates of the parallel devices with complementary control signals. Nevertheless, very large devices typically are required to achieve a sufficiently low "on" resistance of the pass transistors. The use of large MOS devices, however, results in a large input capacitance change between the "on" and "off" states of the T-switch, a large disabled output capacitance of the T-switch, and a substantial charge injection when an output of a crosspoint switches channels. These characteristics limit the fan-in of a crosspoint, i.e., the number of inputs that may be multiplexed into each output of the crosspoint, and may cause distortion and/or noise glitches at the outputs thereof.
Another option for implementing an n:1 multiplexer (for use in an n:m crosspoint) is to selectively enable one of a group of "n" amplifiers (or buffers), with outputs of all "n" amplifiers being connected together and each amplifier receiving a separate input signal. Each of the switched amplifiers in such a configuration thus behaves as a unilateral switch. Since only one amplifier (in each n:1 multiplexer) is on at any one time, power consumption will be minimized in a crosspoint using such switched amplifiers.
If closed-loop "switched" amplifiers are used as unilateral switches, such switches will have a high input impedance and a low on-state output impedance. Because individual closed-loop amplifiers typically are die area intensive, however, the number of closed-loop amplifiers that may be used to implement a switched amplifier multiplexer may be restricted due to die "real estate" concerns. Additionally, the output capacitances of closed-loop amplifiers (in their disabled state) typically are large due to the large output devices employed by the amplifiers. The resulting capacitive loading at the output of any given amplifier thereby places limits on the bandwidth and fan-in of the n:1 multiplexer. Also, the switching time and glitch of an n:1 multiplexer using closed-loop amplifiers are compromised by the large number of devices that must change state when a particular amplifier is enabled or disabled.
If "switched" open-loop buffers are used (instead of closed-loop amplifiers), the resulting unilateral switches also will have a high input impedance and a relatively low output impedance (typically tens of ohms). In contrast with switched closed-loop amplifiers, open-loop buffers are compact (i.e., consume a minimal amount of real estate) and have a low output capacitance when disabled, thereby increasing the fan-in capability of the n:1 multiplexer. Further, relatively "compact" open-loop buffer multiplexers do not suffer from the aforementioned switching time and glitch problems (encountered with switched closed-loop amplifier multiplexers). Disadvantages occur, however, due to the open-loop nature of the buffers. Although the distortion caused by the non-zero output resistance of an open-loop buffer is tolerable when the buffer is driving only a moderate load, when directly driving a video load, a prohibitively high quiescent current would be required to attain low distortion. Although such a gain error problem could be remedied by buffering the output of the open-loop buffer multiplexer with a closed-loop amplifier, such an approach would result in a topology that is more area intensive and less power efficient than even a switched-amplifier approach.
Yet another circuit that can be used to select a single output from a plurality of inputs (i.e., a multiplexer), is a switched-transconductance multiplexer. An example of a switched-transconductance 2:1 multiplexer (configured for unity gain) is shown in FIG. 3. As shown, decoder 30, responsive to a select signal, steers a fixed-tail current to one of two transconductance stages (i.e., either transconductance stage GM0 or transconductance stage GM1), thereby enabling the stage receiving the tail current. The output of the selected transconductance stage is a differential current which, in this example, is converted into a single-ended current by a current mirror comprised of transistors Q115 and Q116 and integrated by capacitor C1 and high-gain amplifier A1. The output of amplifier A1 is buffered by unity gain buffer A2 and fed back to the inverting inputs of both transconductance stages. The high loop-gain of such a switched-transconductance circuit minimizes the error between the selected input and the output.
The switched-transconductance multiplexer topology (such as that shown in FIG. 3) offers several of the advantages offered by switched amplifier multiplexers, i.e., high input impedance, low output impedance, low distortion, high output-drive capability and selectable gain. Additionally, in contrast to the switched amplifier topology, the disabled output capacitance of a switched-transconductance multiplexer also is low (since the multiplexing function is accomplished internally) and only the input stages are replicated, thereby increasing the compactness of the multiplexer. Also, since changing the selected input involves the switching of only a few input devices, switching times are reduced and smaller glitches are encountered than with a switched amplifier architecture. Further, since only one of the transconductance stages is enabled at any given time, the power dissipation of the circuit is little more than that of a single amplifier.
Ideally, signals applied to the inputs of unselected transconductance stages in a switched-transconductance multiplexer would not influence the output of the multiplexer. Parasitic capacitances, however, caused by the wiring of the circuit and the reverse biased junctions of the input transistors in the unselected stages (e.g., transistors Q111 and Q112 in FIG. 3) tend to act as high-pass conduction paths between the unselected inputs and the output of the multiplexer. Although the parasitic capacitance caused by the circuit's wiring may be reduced by optimizing the circuit layout, at high frequencies, the parasitic capacitances of the input transistors in the unselected transconductance stages may still permit undesirable crosstalk between the unselected inputs and the selected input (i.e., crosstalk between channels) which, in turn, places an upper limit on the bandwidth of the switched-transconductance multiplexer.
One circuit designed to reduce the crosstalk between unselected and selected channels in a multiplexer (caused by the parasitic capacitances of input transistors in the unselected transconductance stages) is shown in FIG. 4. As shown, each of transistors Q105 and Q106 comprise one half of a differential pair of input transistors, while both of transistors Q105 and Q106 share transistor Q107 as the second half of each of the respective differential pairs. The signals on each of select lines SEL0 and SEL1 determines which, if either, of transistors Q105 and Q106 is enabled at any given time. That is, if either of select lines SEL0 and SEL1 is asserted (i.e., a logic high signal is placed thereon), then the transistor(s) receiving the logic high signal (i.e., transistor Q103 and/or Q104) will be turned on. If transistor Q103 is turned on, then the biasing current from current source I1 will be steered away from the emitter of transistor Q101, thereby reverse biasing transistors Q101 and Q105. Similarly, if transistor Q104 is turned on, then the biasing current from current source 12 will be steered away from the emitter of transistor Q102, thereby reverse biasing transistors Q102 and Q106. If either of transistors Q103 or Q104 is not turned on, however, then a second half of the differential pair of input transistors (i.e., transistor Q105 or Q106, respectively) will be enabled and an input signal at the base of the emitter follower connected thereto (i.e., transistor Q101 or Q102, respectively) will be processed by the differential pair.
When a particular input is not selected, a corresponding one of transistors Q103 and Q104 will provide a low impedance path from the base of the non-selected one of the differential pair of input transistors to ground. The resulting T-switch-like structure has the advantage of bypassing both the emitter-base and collector-base capacitances of the non-selected input transistor. The presence of emitter followers Q101 and Q102, however, increases the power consumption of the circuit since they must be provided with high bias currents (from current sources I1 and I2, respectively). Additionally, since the biasing currents from current sources I1 and I2 are steered through transistors Q103 and Q104, respectively, when their associated input stage is disabled, these currents are wasted, i.e., they consume power unnecessarily. Moreover, the input followers (i.e., transistors Q101 and Q102) cause an uncompensated voltage offset (i.e., approximately one base-to-emitter voltage drop (Vbe)) to appear between the differential inputs of the circuit and may increase noise and/or decrease the bandwidth of the circuit. Although the voltage offset could be compensated by including a feedback follower in the circuit, such an addition would further increase the power dissipation of the circuit.
It therefore is a general aim of the invention to provide a high-isolation switched transconductance circuit that consumes less power than prior art circuits. It is an additional aim of the invention to provide a switched-transconductance circuit with improved off-state isolation that does not cause a significant voltage offset to appear between the differential inputs of the circuit.